Memory Module Design File Registrations

The JEDEC JC-45 Committee for Memory Modules is responsible for the development, simulation and verification of numerous memory module standards, including various DIMM types such as Unbuffered DIMMs, Registered DIMMs, Buffered DIMMs, Low-Profile DIMMs and SODIMMs. Memory modules produced in accordance with JEDEC memory module standards are widely utilized in computer servers, desktop systems, telecommunication and other consumer and business applications.

For each memory module family developed within JC-45, both a Design Standard and one or more related Memory Module Design File Registrations (sometimes referred to as Gerber Files) linked to from this page have been developed in accordance with the JEDEC Manual of Operation and Procedure. The Design Standards provide detailed information regarding the module design details, as developed and characterized by various JEDEC member companies. These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to downloading files.  Selected design files are only available to non-members for a fee.  All design files are free for JEDEC members to download.

• Design File License Agreement
• Design File Registration Procedure

If you do not find a particular module design configuration and/or speed grade within a recent module family, the module design may still be in-process or undergoing review. JEDEC JC-45 members can download information and/or designs for work-in-progress from the members-only protected area.