Global Standards for the Microelectronics Industry
JEDEC Committee:
JC-16 Interface Technology
The activities within JC-16’s scope include the specification of power supply voltage levels for digital integrated circuits and the definition of electrical interfaces between the components of a system. The committee scope further encompasses interface protocols, modeling, simulation, testing environments, and verification.
JC-16 also hosts efforts on operating environment specifications that are common to JC-40, JC-42, and JC-45. The committee maintains a liaison with other JEDEC committees and appropriate outside organizations, both in formulating standards and in promoting wide acceptance of the committee’s activities.
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Recent Documents
| SERIAL INTERFACE FOR DATA CONVERTERS | JESD204C.01 | Jan 2022 |
| 1.05 V CMOS | JESD8-34 | Apr 2020 |
| POD125 - 1.25 V PSEUDO OPEN DRAIN I/O | JESD8-30A | Jun 2019 |
| 0.5 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL05) | JESD8-33 | Jun 2019 |
| POD135 - 1.35 V PSEUDO OPEN DRAIN I/O | JESD8-21C | Jun 2019 |
| 1.8 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE | JESD8-31 | Mar 2018 |
| 0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06) | JESD8-29 | Dec 2016 |
| MULTI-WIRE MULTI-LEVEL I/O STANDARD | JESD247 | Jun 2016 |
| 300 mV INTERFACE | JESD8-28 | Jun 2015 |
| HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT | JESD8-22B | Apr 2014 |
